1. Field of the Invention
The present invention relates to the encapsulating of semiconductor structures and, in particular, to the producing of encapsulated chips.
2. Description of the Related Art
As it is known, for wafer-level encapsulation, methods are employed to mechanically stabilize wired integrated circuits, to protect the active structures and to achieve the easy construction of high bumps. In a commercially available implementation, with the increasing integration density and compactness of the semiconductor structures, it is being aimed at a wafer-level encapsulation of single integrated circuits with a fan-in redistribution in the range of mean contact distances greater than 400 μm.
FIG. 1 schematically shows depictions illustrating a method in which a wafer 10 with chips disposed thereon is first encapsulated and the encapsulated wafer 10 is then severed along separating lines 12 for producing diced chips 14. As can be seen, the thus obtained chip 14 has an encapsulation layer only on an upper main surface.
FIGS. 2a–c show schematic illustrations of a known chip 18 with a chip-size package. With reference to FIG. 2a, chip 18 has a passivation layer 20 on a main surface on which a copper fan-in redistribution structure 22 is formed. The redistribution structure 22 is connected to respective aluminum pads 26 disposed on edges 24 of chip 18.
The redistribution structure 22 further comprises post structures 28 projecting from the main surface of the chip and provided, on an upper surface, with solder bumps with a BGA pattern (BGA=ball-grid array) or a LGM pattern (LGA=land grid array). The post structures 28 are disposed in a cover layer 32 from a sealing material, e.g. a polymer or EPOXY material, to protect and mechanically stabilize them. FIG. 2b shows a top view onto chip 18 before encapsulation thereof, with the cover layer 32 not yet having been formed. Furthermore, FIG. 2c shows a top view onto the encapsulated chip 18, in which the post structures 28 extending through the cover layer 32 can be recognized in a regular grid arrangement.
It is disadvantageous about the prior-art procedures and methods that there is no possibility for the construction of a system in package in miniaturized implementation. In the prior art, it is also not provided to mount and then encapsulate different chips on wafer level.
The fan-in redistribution used in the prior art, in which outward-leading contacts are disposed, so that they are disposed within a chip footprint, may also lead, with high contact numbers, to an only very low relaxation or enlargement of the mean contact distance. Fan-in redistribution is therefore only partly suited for the requirements occurring with future integration densities.
Furthermore, with a further development in chip technology and a die-shrink resulting therefrom, it is required to change the arrangement of the contact pads, whereby users of such a member have to adapt circuit board layouts and loading processes to the respective members. This is connected with additional cost, and also prevents quick introduction in the market.
In the prior art, various encapsulation methods are used. For the encapsulation of a wafer, for example, it is known from U.S. Pat. No. 6,245,595 B1 to arrange a wafer in a bottom injection mold, a film being applied to the wafer in a coplanar manner to enable sealing the injection molding space. After the film has been brought into direct contact with solder bumps disposed on the wafer, a top injection molding part is pressed onto the film. Then an encapsulation material is injected into the formed cavity with pressure applied, so that an encapsulation layer forms between the wafer and the film, the solder bumps which are in direct contact with the film being substantially free of the encapsulation material on their upper portions. After the production of the encapsulation layer, the film is removed, whereupon the wafer with the encapsulation layer applied thereto is diced to produce separated chips.
This method has the disadvantage that, when creating an encapsulation layer on the entire wafer and subsequently dicing the wafer with the encapsulation layer, the diced chips units have an area that corresponds to the area of the chip. Accordingly, with such a method, no redistribution beyond the area of the semiconductor chip is possible. Furthermore, the method has the disadvantage that an encapsulation layer is only disposed on the main surface of the chips, with the side surfaces forming after the dicing not being encapsulated and therefore having a decreased mechanical protection.
Furthermore, a method is known from EP 1 035 572 A2, in which a resin material in powder or particle form is applied on a surface of a wafer with bumps. The wafer is placed in a cavity of a mold and then heated to melt the resin material. Then a top mold is pressed against a film applied on the bumps, whereby a resin layer forms between the film and the wafer.
Apart from the disadvantages already described above of encapsulating the entire wafer, this method also has the disadvantage of an expensive process sequence, in which first material is applied and then subjected to a melting procedure, wherein also mechanical actuation is required during molding. This results in high production costs and a low production rate for the method.
Another method for creating encapsulation layers is described in U.S. Pat. No. 6,338,980 B1. Prior to the resin sealing process, dicing of a wafer into semiconductor devices is conducted. After conducting the dicing process, the diced chips are arranged on a base member and then subjected to a resin sealing process, wherein the semiconductor devices are applied and mounted to a base support. Then a resin compression molding process is conducted to create a resin layer on the surface of the semiconductor devices and a resin layer between the devices.
In the above method, wherein the chips are diced prior to encapsulation and then arranged on a base support for encapsulation, however, additional steps and devices, such as a chip support or chuck for mounting the chips and transporting them to the base support, are required. Thereby, the expenses in the production thereof increase, so that production costs increase. Furthermore, the use of a resin compression molding process is also disadvantageous for some applications.
Another disadvantage of the prior art is that the integration of functional structures on the encapsulation level is not provided. For example, in the prior art, the shaping of raised contact pads or the creation of geometric structures for assembly assistance, e.g. V-notches, is only achieved by additional material treatment or by additional steps.
It is the object of the present invention to provide a method which enables inexpensive encapsulating of chips with a concurrent, high production rate.